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may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m tisp8200m, buffered p-gate scr dual tisp8201m, buffered n-gate scr dual complementary buffered-gate scrs for dual polarity slic overvoltage protection tisp8200m device symbol high performance protection for slics with +ve & -ve battery supplies tisp8200m, negative overvoltage protector ?wide 0 to -90 v programming range ?low 5 ma max. gate triggering current ?high -150 ma min. holding current tisp8201m, positive overvoltage protector ?wide 0 to +90 v programming range ?low -5 ma max. gate triggering current ?20 ma min. holding current rated for international surge wave shapes how to order tisp8200m d package (top view) description the tisp8200m/tisp8201m combination has been designed to protect dual polarity supply rail monolithic slics (subscriber line interface circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. protection against negative overvoltages is given by the tisp8200m. protection against positive overvoltages is given by the tisp8201m. both parts are in 8-pin small- outline surface mount packages. the tisp8200m has an array of two buffered p-gate scrs with a common anode connection. each scr cathode and gate has a separate terminal connection. the npn buffer transistors reduce the gate supply current. in use, the cathodes of the tisp8200m scrs are connected to the two conductors of the pots line (see applications information). the gates are connected to the appropriate negative voltage battery feed of the slic driving the line conductor pair. this ensures that the tisp8200m protection voltage tracks the slic negative supply voltage. the anode of the tisp8200m is connected to the slic common. surface mount small-outline package 1 2 3 4 5 6 7 8 mdrxakc nc - no internal connection g2 a a g1 k1 k2 nc nc sdrxajb a a g1 g2 k1 k2 tisp8201m device symbol tisp8201m d package (top view) 1 2 3 4 5 6 7 8 mdrxalc nc - no internal connection g2 k k g1 a1 a2 nc nc sdrxakb a1 a2 k k g1 g2 wave shape standard i tsp a 2/10 s telcordia gr-1089-core 210 10/700 s itu-t k.20, k.21 & k.45 70 10/1000 s telcordia gr-1089-core 45 ............................................ ul recognized components *rohs directive 2002/95/ec jan 27 2003 including annex device package carrier tisp8200m d (8-pin small-outline) embossed tape reeled TISP8200MDR tisp8201m d (8-pin small-outline) embossed tape reeled tisp8201mdr TISP8200MDR-s tisp8201mdr-s for standard termination finish order as for lead free termination finish order as *rohs compliant versions available
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. absolute maximum ratings for tisp8200m, t a = 25 c (unless otherwise noted) tisp8200m & tisp8201m description (continued) negative overvoltages are initially clipped close to the slic negative supply by emitter follower action of the npn buffer tran sistor. if sufficient clipping current flows, the scr will regenerate and switch into a low voltage on-state condition. as the overvoltage subsides, the high holding current of the scr prevents d.c. latchup. the tisp8201m has an array of two buffered n-gate scrs with a common cathode connection. each scr anode and gate has a separate terminal connection. the pnp buffer transistors reduce the gate supply current. in use, the anodes of the tisp8201m scrs are connected to the two conductors of the pots line (see applications information). t he gates are connected to the appropriate positive voltage battery feed of the slic driving that line pair. this ensures that the tisp82 01m protection voltage tracks the slic positive supply voltage. the cathode of the tisp8201m is connected to the slic common. positive overvoltages are initially clipped close to the slic positive supply by emitter follower action of the pnp buffer tran sistor. if sufficient clipping current flows, the scr will regenerate and switch into a low voltage on-state condition. as the overvoltage subsides, the slic pulls the conductor voltage down to its normal negative value and this commutates the conducting scr into a reverse biassed condition . rating symbol value unit repetitive pe ak off-stat e voltage, tisp8200m v gk =0 v drm -120 v repetitive pe ak reverse voltage, v ga =-70v v rrm 120 v no n-repetitive peak on-state pulse current, (see notes 1 and 2) i tsp a 10/1000 s( te lcordia/bellcore gr-1089-core, issue 2, february 1999, section 4) -45 5/310 s( i tu-t k.20, k.21& k.45, k.44 open-circuit voltage wave shape 10/700 s) -70 2/10 s( te lc or di a/bellcore gr-1089-core, issue 2, february 1999, section 4) -210 no n-repetitive peak on-state current, 50/60 hz (see notes 1, 2 and 3) i tsm a 100 ms 1s 5s 300 s 900 s -11 -6.5 -3.4 -1.4 -1.3 no n-repetitive peak gate current, 2/10 sp ulse, cathode commoned (see note 1) i gsm 10 a j unction temperature t j -55 to +150 c st or age temperature range t stg -65 to +150 c no te s: 1. initially, the protector must be in thermal equilibrium with -40 c t j 85 c. t he surge may be repeated after the device returns to it s initial conditions. 2. these non-repetitive rated currents are peak values. the rated current values may be applied to any cathode-anode terminal pa ir. abov e 85 c, derate linearly to zero at 150 c lead temperature. 3. these non-repetitive rated terminal currents are for the tisp8200m and tisp8201m together. device (a) terminal positive curre nt va l ues are conducted by the tisp8201m and (k) terminal negative current values by the tisp8200m.
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m recommended operating conditions absolute maximum ratings for tisp8201m, t a = 25 c (unless otherwise noted) rating symbol value unit repetitive pe ak off-st ate voltage, v ga =0 v drm 120 v repetitive pe ak reverse voltage, v gk =70v v rrm -120 v no n-repetitive peak on-state pulse current, (see notes 1 and 2) i tsp a 10/1000 s( te lcordia (bellcore) gr-1089-core, issue 2, february 1999, section 4) 45 5/310 s( i tu-t k.20, k.21& k.45, k.44 open-circuit voltage wave shape 10/700 s) 70 2/10 s( te lcordia (bellcore) gr-1089-core, issue 2, february 1999, section 4) 210 no n-repetitive peak on-state current, 50/60 hz (see notes 1, 2 and 3) i tsm a 100 ms 1s 5s 300 s 900 s 11 6.5 3.4 1.4 1.3 no n-repetitive peak gate current, 2/10 sp ulse, cathode commoned (see note 1) i gsm -10 a j unction temperature t j -55 to +150 c st or age temperature range t stg -65 to +150 c no te s: 1. initially, the protector must be in thermal equilibrium with -40 c t j 85 c. t he surge may be repeated after the device returns to it s initial conditions. 2. these non-repetitive rated currents are peak values. the rated current values may be applied to any cathode-anode terminal pa ir. abov e 85 c, derate linearly to zero at 150 c lead temperature. 3. these non-repetitive rated terminal currents are for the tisp8200m and tisp8201m together. device (a) terminal positive curre nt va l ues are conducted by the tisp8201m and (k) terminal negative current values by the tisp8200m. see figure 10 min typ max unit c1, c2 gate decoupling capacitor 100 220 nf r1, r2 series resistance for telcordia gr-1089-core first-level and second-level surge survival se ri es re si st ance for itu-t k.20, k.21 and k.45 coordination with a 400 v primary protector 15 10 20 20 ?
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m electrical characteristics for tisp8200m, t a = 25 c (unless otherwise noted) thermal characteristics parame ter test conditions min typ max unit i d o ff- st ate current v d =v drm , v gk =0 t j =0 c-5 a t j =85 c -50 a i r re v erse current v r =v rrm , v ga =-70v t j =0 c5 a t j =85 c50 a v (bo) br eakover voltage dv/dt = -250 v/ms, source resistance = 300 ? , v ga = -80 v -82 v v (bo) br eakover voltage 2/10 waveshape, (i k ) i t =- 100 a, di/dt max. = -58 a/ s, v ga =-80v -95 v i h hold ing current (i k ) i t =-1a, di/dt = 1 a/ms, v ga = -80 v -150 ma i gt ga te trigger current (i k ) i t =-5a, t p(g) 20 s, v ga =-80v 5 ma c off o ff- st ate capacitance f = 1 mhz, v d =1v, v ga =- 80 v, (see note 4) v d =0 35 pf v d =-5v 20 v d =-50v 10 no te 4: these capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. the unmeasured device terminals are a.c. connected to the guard terminal of the bridge. electrical characteristics for tisp8201m, t a = 25 c (unless otherwise noted) parame ter test conditions min typ max unit i d of f- st ate current v d =v drm , v ga =0 t j =0 c5 a t j =85 c50 a i r re v erse current v r =v rrm , v gk =70v t j =0 c-5 a t j =85 c -50 a v (bo) br eakover voltage dv/dt = 250 v/ms, source resistance = 300 ? , v gk =80v 82 v v (bo) br eakover voltage 2/10 waveshape, (i a ) i t = 100 a, di/dt max. = 58 a/ s, v gk =80v 95 v i h hold ing current (i a ) i t =1a, di/dt = -1 a/ms, v gk =80v +20 ma i gt ga te trigger current (i a ) i t =5a, t p(g) 20 s, v gk =80v -5 ma c off o ff- st ate capacitance f = 1 mhz, v d =1v, v gk =80v, (s ee note 4) v d =0 35 pf v d =5v 20 v d =50v 10 no te 4: these capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. the unmeasured device terminals are a.c. connected to the guard terminal of the bridge. p arameter t est conditions min typ max unit r ja j unction to free air thermal resistance p tot =0.52w, t a =70 c, 5 cm 2 , fr 4 pcb 160 c/w
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. parameter measurement information tisp8200m & tisp8201m figure 1. tisp8200m ka terminal characteristic quadrant i blocking ch aracteristic quadrant iii switching ch aracteristic +v -v v ga v d i h i tsm i tsp v (bo) i d +i -i v gk(bo) v rrm v r i r i rrm pm8xacb figure 2. tisp8201m ak terminal characteristic -v v gk v d v (bo) i h i tsm i tsp i d quadrant iii blocking ch aracteristic +i -i quadrant i switching ch aracteristic v ga(bo) v rrm v r i r i rrm +v pm8xabb
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m applications information operation of slics using positive and negative voltage supply rails figure 3 shows a typical powering arrangement for a multi-supply rail slic. v batr is a positive supply and v batl and v bath are negative supplies. v bath is more negative than v batl . with the positive and negative supply switches s2 and s1 in the positions shown, the line driver amplifiers are powered between 0 v and v batl . this mode minimizes the power consumption for short loop transmission. for long loops, the driver voltage is increased by operating s1 to connect v bath . to generate ringing, s2 is operated to apply v batr , powering the drivers from a total supply voltage of v batr - v bath . these conditions are shown in figure 4. fig ure 4. driver su pply voltage levels 0 v v batl short l oop v bath 0 v long loop v dcring v slicr v pkring /2 v slich v batr ai8xag v bath vv - batr bath ringing v pkring /2 v pkring /2 v pkring /2 conventional ringing is typically unbalanced ground or battery backed. to minimize the supply voltage required, most multi-rail slics use balanced ringing as shown in figure 4. the ringing has d.c., v dcring , and a.c., v pkring , components. a 70 v rms a.c. ring signal has a peak value, v pkring , of 99 v. if the d.c. component was 20 v, then the total voltage swing needed would be 99 + 20 = 119 v. there are internal losses in the slic from the positive supply, v slicr , and the negative supply, v slich . the sum of these two losses generally amounts to a total of 10 v. this makes a total supply rail value of 119 + 10 = 129 v. in practice, the voltage might be distributed as v batr = +60 v and v bath = -70 v. these values are nominal and some extra voltage should be provided to cover power supply voltage tolerance. figure 3. slic w ith voltage supply switching s1 line drivers v bath s2 0 v v batr slic ai8xaf supply switches line v batl
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m slic parameter values the table below shows some details of currently available slics using positive and negative supply rails. manufacturer infineon legerity unit slic series slic-s slic-e islic slic # peb4264 peb 4265 79r251 data sheet issue 14/07/2000 14/07/2000 -/08/2000 short circuit current 130 130 150 ma v bath max. -70 -90 -85 v v batr max. +50 +90 +85 v v batr -v ba th max. 90 160 150 v ac ri nging for: 45 85 65 v rms v bath -54 -70 -68 v v batr +36 +80 +52 v v batr -v bath 90 150 120 v r or t power max. < 10 ms tba 10 w r or t overshoot < 10 ms -5 5 v r or t overshoot < 1 ms -10 +10 -10 +10 v r or t overshoot < 10 s-10 +30 - 10 +30 v r or t overshoot < 1 s-10 10 v r or t overshoot < 250 ns -15 15 v line feed resistance 20 + 30 20 + 30 50 ? ?legerity, the legerity logo and islic are the trademarks of legerity, inc. (formerly amds communication products division). other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. the maximum total voltage, v batr - v bath , is normally about 10 % less than the sum of the maximum v batr and maximum v bath values. in terms of voltage overshoot, 10 v is needed for 1 s and 15 v for 250 ns. it is important to define the protector overshoot under actual circuit conditions. for example, if the series line feed resistor was 20 ? , r1 in figure 10, and telcordia gr-1089-core 2/10 and 10/1000 first level impulses were applied, the peak protector currents would be 100 a and 33 a. therefore, the protector voltage overshoot sh ould be measured at 100 a, 2/10 and 33 a, 10/1000. using the table values for maximum battery voltage and minimum overshoot gives a requirement of 105 v from the output to ground and 175 v between outputs. there needs to be temperature guard banding for the change in protector characteristics with temperature . to cover down to -40 c, the 25 c protector minimum values become 120 v referenced to ground, 190 v between outputs and 100 v or -100 v on the gate. operation of gated protectors figure 5 shows how the tisp8200m and tisp8201m limit overvoltages. the tisp8200m scr sections limit negative overvoltages and t he tisp8201m scr sections limit positive overvoltages. the tisp8200m (buffered) gate is connected to the negative slic battery feed voltage (v bath ) to provide the protection reference voltage. negative overvoltages are initially clipped close to the slic negative supply rail value (v bath ) by the conduction of the tisp8200m transistor base-emitter and the scr gate-cathode junctions. if sufficient current is available from the overvoltage, then the scr will cro wbar into a low voltage ground referenced on-state condition. as the overvoltage subsides, the high holding current of the scr prevents d.c. la tchup with the slic output current.
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m the negative protection voltage, v (bo) , will be the sum of the gate supply (v bath ) and the tisp8200m peak gate(terminal)-cathode voltage (v gt ). under a.c. overvoltage conditions v gt will be less than 2.0 v. the integrated transistor buffer in the tisp8200m greatly reduces protectors source and sink current loading on the v bath supply. without the transistor, the scr gate current would charge the v bath supply. an electronic power supply is not usually designed to be charged like a battery. as a result, the electronic supply would switc h off and the scr gate current would provide the slic supply current. normally the slic current would be less than the gate current, which would cause the supply voltage to increase and destroy the slic by a supply overvoltage. older designs using just scrs needed to incorporate a sacrificial zener diode across the supply line to go short if the supply voltage increased too much. the integrated transistor buffer remov es the charging problem and the need for a safety zener. fast rising impulses will cause short term overshoots in gate-cathode voltage. the negative protection voltage under impulse co nditions will also be increased if there is a long connection between the gate decoupling capacitor, c1, and the gate terminal. during the in itial rise of a fast impulse, the gate current (i g ) is the same as the cathode current (i k ). rates of 60 a/ s can cause inductive voltages of 0.6 v in 2.5 cm of printed wiring track. to minimize this inductive voltage increase of protection voltage, the length of the capacitor to gate te rminal tracking should be minimized. the tisp8201m (buffered) gate is connected to the positive slic battery feed voltage (v batr ) to provide the protection reference voltage. positive overvoltages are initially clipped close to the slic positive supply rail value (v batr ) by the conduction of the tisp8201m transistor base-emitter and the scr gate-anode junctions. if sufficient current is available from the overvoltage, then the scr will crowb ar into a low voltage ground referenced on-state condition. as the overvoltage subsides the slic pulls the conductor voltage down to its norm al negative value and this commutates the conducting scr into a reverse biassed condition. operation of gated protectors (continued) vo ltage stress levels on the tisp8200m and tisp8201m figure 6 shows the protector electrodes. the package terminal designated gate, g, is the transistor base, b, electrode connecti on and so is marked as b (g). the following junctions are subject to voltage stress: transistor eb and cb, scr ak (reverse and off state). t his clause covers the necessary testing to ensure the junctions are good. t esting transistor eb and scr ak reverse: the highest reverse eb voltage and reverse ak voltage occurs during the overshoot period of the other protector. for the tisp8200m, the scr has v batr plus the tisp8201m overshoot above v batr . the transistor eb has an additional v bath voltage applied (see figure 7). the reverse current, i r , flowing into the k terminal will be the sum of the transistor i eb and the actual internal scr i r . the reverse voltage applied to the k terminal is the tisp8201m protection voltage, v (bo) (v batr plus overshoot), and the g terminal has v bath . similarly for the tisp8201m, i r is measured with the tisp8200m v (bo) applied and it is the sum of the transistor i eb and the actual internal scr i r . v batr is applied to the g terminal. figure 5. overvoltage conditions c1 100 nf i g slic v bath tisp 8200m i k c2 100 nf v batr 0 v 0 v i g i a ring tip ai8xad tisp 8201m
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m fi gure 6. protector electrodes v bath tisp 8200m v batr 0 v ai8xah tisp 8201m 0 v ring or tip a ke c b (g) ae c b (g) k figure 7. reverse current verification v bath tisp 8200m ai8xaj 0 v k b (g) i eb i r (internal) v batr 0 v tisp 8201m a b (g) i eb i r v (bo) 8201m i r (internal) i r v (bo) 8200m fi gure 8. off-state current verification tisp 8200m 0 v ai8xak tisp 8201m 0 v k b (g) a i cb i d i cb v (bo) 8201m v (bo) 8200m i d (internal) i d (internal) i d b (g) t esting transistor cb and scr ak off state: the highest ak voltage occurs during the overshoot period of the protector. to make sure that the scr blocking junction does not break down during this period, a d.c. test for off-state current can be applied at the overshoot voltage value. to avoid transistor cb current amplification by the transistor gain, the transistor base-emitter is shorted during this test (s ee figure 8). summary: tw o tests are needed to verify the protector junctions. maximum current values for i r and i d are required. vo ltage stress levels on the tisp8200m and tisp8201m (continued)
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m figure 9. voltage overshoot referenced to gate bias voltage ti sp8200m 2/10 overshoot time - ns 0 100 200 300 400 500 600 700 800 900 1000 o vershoot voltage - v -20 -10 0 10 20 ai8xama (i k ) i t = -100 a v ga = -80 v ti sp8201m 2/10 overshoot time - ns 0 100 200 300 400 500 o vershoot vol tage - v -20 -10 0 10 20 ai8xana (i a ) i t = +100 a v gk = +80 v figure 10. line protection with tisp8200m and tisp8201m c1 100 nf slic v bath c2 100 nf v batr 0 v 0 v tisp 8201m ring tip r1 gr-108 9-core r1 = 15 ? ? ? ? min. (1 st & 2 nd level) itu-t k.20 & k.21 r1 = 10 ? ? ? ? min for co ordina tion r1 tisp 8200m ai8xae figure 9 shows typical overshoots on a 100 a 2/10 waveshape. both devices are under 10 v peak, which meets the needs of the sli cs listed earlier. tisp8200m and tisp8201m voltage overshoot figure 10 shows a typical circuit for single line protection using one tisp8200m and one tisp8201m. the series resistor values limit the test impulse currents to within the protector ratings. line protection with tisp8200m and tisp8201m
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. tisp8200m & tisp8201m mechanical data device symbolization code devices are coded as below. device symbolization tisp8200m 8200m tisp8201m 8201m
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical data d008 plastic small outline package this small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. the compou nd will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated i n high humidity conditions. leads require no additional cleaning or processing when used in soldered assembly. tisp8200m & tisp8201m notes: a. l eads are within 0.25 (0.010) radius of true position at maximum material condition. b. body dime nsions do not include mold flash or protrusion. c. mold flas h or protrusion shall not exceed 0.15 (0.006). d. l ead tips to be planar within 0.051 (0 .002). md xxaae 5. 80 - 6. 20 (0.228 - 0. 2 44) 4. 80 - 5. 00 (0.189 - 0. 19 7) d008 8 765 4 3 2 1 3. 81 - 4. 00 (0.150 - 0. 1 57) 7 nom 3 p la ces 7 nom 4 p la ces 4 4 0. 28 - 0.79 (0.011 - 0. 03 1) 0. 10 2 - 0.203 (0.004 - 0. 008) 8-pin small outline microelectronic standard pa ck ag e ms-012, jedec publication 95 x 45 nom 0. 19 0 - 0.229 (0.007 5 - 0. 00 90) index pin spacing 1. 27 (0.050) (see note a) 6 p laces 1. 35 - 1.75 (0.053 - 0. 069) 0. 36 - 0.51 (0.014 - 0. 020) 8 p laces 0. 51 - 1.12 (0.020 - 0. 044) 0. 25 - 0.50 (0.010 - 0. 020) 4. 60 - 5.21 (0.181 - 0. 205) dimensions are: millimeters (inches)
may 1998 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. mechanical data tisp8200m & tisp8201m d008 tape dimensions d008 package (8-pin small outline) single-sprocket tape 7. 90 - 8.10 (.31 1 - .319) 3. 90 - 4.10 (. 154 - .161 ) 1. 95 - 2.05 (.07 7 - .081) 1. 50 - 1.60 (. 059 - .063 ) 5. 40 - 5.60 (. 213 - .220 ) 11 .70 - 12.30 (. 461 - .484 ) 0 min . 6. 30 - 6. 50 (.24 8 - .256) 0. 40 (.01 6) 2. 0 - 2.2 (. 079 - .087 ) direct i on of feed carrie r ta pe embossment cover ta pe notes: a. ta ped devices are supplied on a reel of the following dimensions:- reel diam eter: reel hub diameter: reel axial hole: b. 2500 devices are on a reel. mdxxatc min . 1. 5 (.05 9) min . 0. 8 (.0 3) 330 +0.0/- 4.0 (12.99 + 0.0 /-.1 57) 13.0 0.2 (.51 2 .008) 10 0 2. 0 (3.937 .07 9) ?isp?is a trademark of bourns, ltd., a bourns company, and is registered in u.s. patent and trademark office. ?ourns?is a registered trademark of bourns, inc. in the u.s. and other countries.

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